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| author | Peter Maydell | 2018-01-25 17:24:55 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-01-25 17:24:56 +0100 |
| commit | a3f9362af5c7071036fafb66665b85fda1e49bcc (patch) | |
| tree | bc66805eb2a71797d9146c1f8590f184bf24ff11 /hw/sparc64/trace-events | |
| parent | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180125-pull-request' ... (diff) | |
| parent | sun4u: implement power device (diff) | |
| download | qemu-a3f9362af5c7071036fafb66665b85fda1e49bcc.tar.gz qemu-a3f9362af5c7071036fafb66665b85fda1e49bcc.tar.xz qemu-a3f9362af5c7071036fafb66665b85fda1e49bcc.zip | |
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging
qemu-sparc update
# gpg: Signature made Thu 25 Jan 2018 13:44:58 GMT
# gpg: using RSA key 0x5BC2C56FAE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* remotes/mcayland/tags/qemu-sparc-signed:
sun4u: implement power device
sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events
sabre: convert from SABRE_DPRINTF macro to trace-events
apb: rename apb.c to sabre.c
sun4u: rename apb variables and constants
apb: rename QOM type from TYPE_APB to TYPE_SABRE
apb: QOMify sabre PCI host bridge
apb: change pbm_pci_host prefix functions to use sabre_pci prefix
apb: rename APB functions to use sabre prefix
simba: rename PBMPCIBridge and QOM types to reflect simba naming
apb: split simba PCI bridge into hw/pci-bridge/simba.c
sparc/leon3 irqmp: fix IRQ software ack
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sparc64/trace-events')
| -rw-r--r-- | hw/sparc64/trace-events | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index 2ee2d75f70..ce597a6e9d 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -7,3 +7,21 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d" sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d" sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64 + +# hw/sparc64/sparc64.c +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" +sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" +sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" +sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" +sparc64_cpu_tick_irq_fire(void) "tick_irq: fire" +sparc64_cpu_stick_irq_disabled(void) "stick_irq: softint disabled" +sparc64_cpu_stick_irq_fire(void) "stick_irq: fire" +sparc64_cpu_hstick_irq_disabled(void) "hstick_irq: softint disabled" +sparc64_cpu_hstick_irq_fire(void) "hstick_irq: fire" +sparc64_cpu_tick_set_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s set_count count=0x%"PRIx64" (npt %s) p=%p" +sparc64_cpu_tick_get_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s get_count count=0x%"PRIx64" (npt %s) p=%p" +sparc64_cpu_tick_set_limit(const char *name, uint64_t real_limit, const char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit=0x%"PRIx64 " (%s) p=%p called with limit=0x%"PRIx64" at 0x%"PRIx64" (delta=0x%"PRIx64")" +sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=ZERO - not starting timer" |