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| author | Víctor Colombo | 2022-05-04 23:05:41 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza | 2022-05-05 20:36:17 +0200 |
| commit | bf3dd1e6d0d7c5c4906f89776e15dddc22af784b (patch) | |
| tree | 696cb00a00b9bbd23b650af483041cb0922fc996 /hw/sparc | |
| parent | target/ppc: Add unused msr bits FIELDs (diff) | |
| download | qemu-bf3dd1e6d0d7c5c4906f89776e15dddc22af784b.tar.gz qemu-bf3dd1e6d0d7c5c4906f89776e15dddc22af784b.tar.xz qemu-bf3dd1e6d0d7c5c4906f89776e15dddc22af784b.zip | |
target/ppc: Change MSR_* to follow POWER ISA numbering convention
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.
Add a macro to be used to convert from QEMU order to ISA order.
This solution requires less changes than to use the already defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-23-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/sparc')
0 files changed, 0 insertions, 0 deletions