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| author | Francisco Iglesias | 2017-12-13 18:59:22 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-12-13 18:59:22 +0100 |
| commit | 2e1cf2c9685978193ef429cdb711bf50debea9d8 (patch) | |
| tree | f0bfd476d14257ad9a6b6f5587581b4346f89b61 /hw/ssi/xilinx_spips.c | |
| parent | xilinx_spips: Add support for 4 byte addresses in the LQSPI (diff) | |
| download | qemu-2e1cf2c9685978193ef429cdb711bf50debea9d8.tar.gz qemu-2e1cf2c9685978193ef429cdb711bf50debea9d8.tar.xz qemu-2e1cf2c9685978193ef429cdb711bf50debea9d8.zip | |
xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done
Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20171126231634.9531-12-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/xilinx_spips.c')
| -rw-r--r-- | hw/ssi/xilinx_spips.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ab54da8aa3..3805d8b46d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state == SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask = IXR_ALL; |