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| author | Luc MICHEL | 2017-04-28 14:56:32 +0200 |
|---|---|---|
| committer | Michael Tokarev | 2017-06-04 17:42:55 +0200 |
| commit | 95e9a242e2a393c7d4e5cc04340e39c3a9420f03 (patch) | |
| tree | 1af7bd97b8a1b97d545549896b1fa24534bf5213 /hw/xtensa/sim.c | |
| parent | block: Correct documentation for BLOCK_WRITE_THRESHOLD (diff) | |
| download | qemu-95e9a242e2a393c7d4e5cc04340e39c3a9420f03.tar.gz qemu-95e9a242e2a393c7d4e5cc04340e39c3a9420f03.tar.xz qemu-95e9a242e2a393c7d4e5cc04340e39c3a9420f03.zip | |
target/arm: add data cache invalidation cp15 instruction to cortex-r5
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.
Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw/xtensa/sim.c')
0 files changed, 0 insertions, 0 deletions