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| author | Max Filippov | 2019-01-24 04:26:52 +0100 |
|---|---|---|
| committer | Max Filippov | 2019-01-24 19:44:26 +0100 |
| commit | fa92bd4af71bed76bf57bb1c8b5465414a52ab3f (patch) | |
| tree | 3beaed635eff3b55e6d6809aa579547c748e68af /hw/xtensa | |
| parent | hw/xtensa: xtfpga: use core frequency (diff) | |
| download | qemu-fa92bd4af71bed76bf57bb1c8b5465414a52ab3f.tar.gz qemu-fa92bd4af71bed76bf57bb1c8b5465414a52ab3f.tar.xz qemu-fa92bd4af71bed76bf57bb1c8b5465414a52ab3f.zip | |
target/xtensa: fix access to the INTERRUPT SR
INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected.
Use atomic operations to change INTSET SR.
Fix wsr.intset so that it soesn't clear any bits.
Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'hw/xtensa')
| -rw-r--r-- | hw/xtensa/pic_cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index 0e812d7f06..7e4c65e5ec 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -68,9 +68,9 @@ static void xtensa_set_irq(void *opaque, int irq, int active) uint32_t irq_bit = 1 << irq; if (active) { - env->sregs[INTSET] |= irq_bit; + atomic_or(&env->sregs[INTSET], irq_bit); } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) { - env->sregs[INTSET] &= ~irq_bit; + atomic_and(&env->sregs[INTSET], ~irq_bit); } check_interrupts(env); |