diff options
| author | Joe Komlodi | 2020-11-17 00:11:01 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-15 14:39:30 +0100 |
| commit | 09414144cd3860243aab7e0d20d67c5bd91c1986 (patch) | |
| tree | e33fecf86d6a24f1312ec3b40d0945d7c4ea916f /hw | |
| parent | hw/misc/zynq_slcr: Avoid #DIV/0! error (diff) | |
| download | qemu-09414144cd3860243aab7e0d20d67c5bd91c1986.tar.gz qemu-09414144cd3860243aab7e0d20d67c5bd91c1986.tar.xz qemu-09414144cd3860243aab7e0d20d67c5bd91c1986.zip | |
hw/block/m25p80: Make Numonyx config field names more accurate
The previous naming of the configuration registers made it sound like that if
the bits were set the settings would be enabled, while the opposite is true.
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-2-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/block/m25p80.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index d09a811767..bad7253838 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -136,7 +136,7 @@ typedef struct FlashPartInfo { #define VCFG_WRAP_SEQUENTIAL 0x2 #define NVCFG_XIP_MODE_DISABLED (7 << 9) #define NVCFG_XIP_MODE_MASK (7 << 9) -#define VCFG_XIP_MODE_ENABLED (1 << 3) +#define VCFG_XIP_MODE_DISABLED (1 << 3) #define CFG_DUMMY_CLK_LEN 4 #define NVCFG_DUMMY_CLK_POS 12 #define VCFG_DUMMY_CLK_POS 4 @@ -144,9 +144,9 @@ typedef struct FlashPartInfo { #define EVCFG_VPP_ACCELERATOR (1 << 3) #define EVCFG_RESET_HOLD_ENABLED (1 << 4) #define NVCFG_DUAL_IO_MASK (1 << 2) -#define EVCFG_DUAL_IO_ENABLED (1 << 6) +#define EVCFG_DUAL_IO_DISABLED (1 << 6) #define NVCFG_QUAD_IO_MASK (1 << 3) -#define EVCFG_QUAD_IO_ENABLED (1 << 7) +#define EVCFG_QUAD_IO_DISABLED (1 << 7) #define NVCFG_4BYTE_ADDR_MASK (1 << 0) #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) @@ -769,7 +769,7 @@ static void reset_memory(Flash *s) s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) != NVCFG_XIP_MODE_DISABLED) { - s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; + s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; } s->volatile_cfg |= deposit32(s->volatile_cfg, VCFG_DUMMY_CLK_POS, @@ -784,10 +784,10 @@ static void reset_memory(Flash *s) s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { - s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; + s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; } if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { - s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; + s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; } if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { s->four_bytes_address_mode = true; |