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| author | Peter Crosthwaite | 2013-04-03 06:52:21 +0200 |
|---|---|---|
| committer | Peter Maydell | 2013-04-05 18:03:01 +0200 |
| commit | 1db8b5efe0c2b5000e50691eea61264a615f43de (patch) | |
| tree | dba62b8901afbe8ffb2bf88abe641fc6038feab3 /hw | |
| parent | pl330: Don't inhibit ES bits on INTEN (diff) | |
| download | qemu-1db8b5efe0c2b5000e50691eea61264a615f43de.tar.gz qemu-1db8b5efe0c2b5000e50691eea61264a615f43de.tar.xz qemu-1db8b5efe0c2b5000e50691eea61264a615f43de.zip | |
cadence_uart: Flush queued characters on reset
Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.
Cc: Wendy Liang <jliang@xilinx.com>
Cc: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Jason Wu <huanyu@xilinx.com>
Message-id: 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/cadence_uart.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c index 5426f10018..421ec998d6 100644 --- a/hw/cadence_uart.c +++ b/hw/cadence_uart.c @@ -157,6 +157,7 @@ static void uart_rx_reset(UartState *s) { s->rx_wpos = 0; s->rx_count = 0; + qemu_chr_accept_input(s->chr); s->r[R_SR] |= UART_SR_INTR_REMPTY; s->r[R_SR] &= ~UART_SR_INTR_RFUL; |