diff options
| author | Beniamino Galvani | 2014-03-25 19:22:06 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-04-17 22:34:06 +0200 |
| commit | 323a8771cfb96ab752c9d27e939a2fbac1380b1c (patch) | |
| tree | bd2059a391b50b27945adacb1057022121461e2a /hw | |
| parent | allwinner-a10-pic: fix behaviour of pending register (diff) | |
| download | qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.tar.gz qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.tar.xz qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.zip | |
allwinner-a10-pit: avoid generation of spurious interrupts
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1395771730-16882-4-git-send-email-b.galvani@gmail.com
[PMM: avoid duplicate typedef of AwA10PITState]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/timer/allwinner-a10-pit.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b27fce8cd2..696b7d9977 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -193,18 +193,17 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10PITState *s = AW_A10_PIT(opaque); - uint8_t i; + AwA10TimerContext *tc = opaque; + AwA10PITState *s = tc->container; + uint8_t i = tc->index; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - if (s->control[i] & AW_A10_PIT_TIMER_EN) { - s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; - } - qemu_irq_pulse(s->irq[i]); + if (s->control[i] & AW_A10_PIT_TIMER_EN) { + s->irq_status |= 1 << i; + if (s->control[i] & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i]); + s->control[i] &= ~AW_A10_PIT_TIMER_EN; } + qemu_irq_pulse(s->irq[i]); } } @@ -223,7 +222,11 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - bh[i] = qemu_bh_new(a10_pit_timer_cb, s); + AwA10TimerContext *tc = &s->timer_context[i]; + + tc->container = s; + tc->index = i; + bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); s->timer[i] = ptimer_init(bh[i]); ptimer_set_freq(s->timer[i], 240000); } |