diff options
| author | Mark Cave-Ayland | 2018-06-13 10:30:14 +0200 |
|---|---|---|
| committer | David Gibson | 2018-06-16 08:32:33 +0200 |
| commit | 32a8c27b5dfc834abf7ada7c55fcc69c97ae0140 (patch) | |
| tree | ce1b05d5660ab20bf73fd563ecc65a0382c02125 /hw | |
| parent | mos6522: only clear the shift register interrupt upon write (diff) | |
| download | qemu-32a8c27b5dfc834abf7ada7c55fcc69c97ae0140.tar.gz qemu-32a8c27b5dfc834abf7ada7c55fcc69c97ae0140.tar.xz qemu-32a8c27b5dfc834abf7ada7c55fcc69c97ae0140.zip | |
mos6522: remove additional interrupt flag filter from mos6522_update_irq()
The datasheet indicates that the interrupt is generated by ANDing the
interrupt flags register (IFR) with the interrupt enable register (IER)
but currently there is an extra filter for the SR and timer interrupts.
Remove this extra filter to allow interrupts to be generated by external
inputs on bits 1 and 2 of ports A and B.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/misc/mos6522.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index ad5041d8c0..8d5b419825 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -40,7 +40,7 @@ static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, static void mos6522_update_irq(MOS6522State *s) { - if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { + if (s->ifr & s->ier) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); |