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| author | Philippe Mathieu-Daudé | 2020-09-10 09:01:29 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2020-12-10 18:15:04 +0100 |
| commit | 357088b1ed241566551631a89f55b7c30c4403d6 (patch) | |
| tree | aacee9c063ae16f48a9b7b24e2439ca060826167 /hw | |
| parent | hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink (diff) | |
| download | qemu-357088b1ed241566551631a89f55b7c30c4403d6.tar.gz qemu-357088b1ed241566551631a89f55b7c30c4403d6.tar.xz qemu-357088b1ed241566551631a89f55b7c30c4403d6.zip | |
hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200910070131.435543-5-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/net/xilinx_axienet.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 9bccbe9be3..990ff3a1c2 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -45,11 +45,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET) -typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; -DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM, +typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink; +DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM, TYPE_XILINX_AXI_ENET_DATA_STREAM) -DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_CONTROL_STREAM, +DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_CONTROL_STREAM, TYPE_XILINX_AXI_ENET_CONTROL_STREAM) /* Advertisement control register. */ @@ -310,7 +310,7 @@ struct TEMAC { }; -struct XilinxAXIEnetStreamSlave { +struct XilinxAXIEnetStreamSink { Object parent; struct XilinxAXIEnet *enet; @@ -322,8 +322,8 @@ struct XilinxAXIEnet { qemu_irq irq; StreamSink *tx_data_dev; StreamSink *tx_control_dev; - XilinxAXIEnetStreamSlave rx_data_dev; - XilinxAXIEnetStreamSlave rx_control_dev; + XilinxAXIEnetStreamSink rx_data_dev; + XilinxAXIEnetStreamSink rx_control_dev; NICState *nic; NICConf conf; @@ -856,7 +856,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len, bool eop) { int i; - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); XilinxAXIEnet *s = cs->enet; assert(eop); @@ -877,7 +877,7 @@ static size_t xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, bool eop) { - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj); XilinxAXIEnet *s = ds->enet; /* TX enable ? */ @@ -951,8 +951,8 @@ static NetClientInfo net_xilinx_enet_info = { static void xilinx_enet_realize(DeviceState *dev, Error **errp) { XilinxAXIEnet *s = XILINX_AXI_ENET(dev); - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM( &s->rx_control_dev); object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", @@ -1043,7 +1043,7 @@ static const TypeInfo xilinx_enet_info = { static const TypeInfo xilinx_enet_data_stream_info = { .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, .parent = TYPE_OBJECT, - .instance_size = sizeof(XilinxAXIEnetStreamSlave), + .instance_size = sizeof(XilinxAXIEnetStreamSink), .class_init = xilinx_enet_data_stream_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SINK }, @@ -1054,7 +1054,7 @@ static const TypeInfo xilinx_enet_data_stream_info = { static const TypeInfo xilinx_enet_control_stream_info = { .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, .parent = TYPE_OBJECT, - .instance_size = sizeof(XilinxAXIEnetStreamSlave), + .instance_size = sizeof(XilinxAXIEnetStreamSink), .class_init = xilinx_enet_control_stream_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SINK }, |