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| author | Alex Bennée | 2022-11-21 12:45:13 +0100 |
|---|---|---|
| committer | Peter Maydell | 2022-11-21 12:45:13 +0100 |
| commit | 3d5af538a4fa8456a7e54b8115afe3d6358c1ce5 (patch) | |
| tree | 6cac7a18d7474d2241de18cdbb41c883498ce856 /hw | |
| parent | hw/intc: clean-up access to GIC multi-byte registers (diff) | |
| download | qemu-3d5af538a4fa8456a7e54b8115afe3d6358c1ce5.tar.gz qemu-3d5af538a4fa8456a7e54b8115afe3d6358c1ce5.tar.xz qemu-3d5af538a4fa8456a7e54b8115afe3d6358c1ce5.zip | |
hw/intc: add implementation of GICD_IIDR to Arm GIC
a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
this for the CPU interface register. The fact we don't implement it
shows up when running Xen with -d guest_error which is definitely
wrong because the guest is perfectly entitled to read it.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/arm_gic.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1a04144c38..7a34bc0998 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) /* GICD_TYPER byte 1 */ return (s->security_extn << 2); } - if (offset < 0x08) + if (offset == 8) { + /* GICD_IIDR byte 0 */ + return 0x3b; /* Arm JEP106 identity */ + } + if (offset == 9) { + /* GICD_IIDR byte 1 */ + return 0x04; /* Arm JEP106 identity */ + } + if (offset < 0x0c) { + /* All other bytes in this range are RAZ */ return 0; + } if (offset >= 0x80) { /* Interrupt Group Registers: these RAZ/WI if this is an NS * access to a GIC with the security extensions, or if the GIC |