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| author | Cédric Le Goater | 2018-09-25 15:02:33 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-09-25 16:13:24 +0200 |
| commit | 3d9bada2408329269424628a3be6340c6c28de0e (patch) | |
| tree | 42e4def4d497143af54aa33650f1f54f4dabaea7 /hw | |
| parent | aspeed/timer: fix compile breakage with clang 3.4.2 (diff) | |
| download | qemu-3d9bada2408329269424628a3be6340c6c28de0e.tar.gz qemu-3d9bada2408329269424628a3be6340c6c28de0e.tar.xz qemu-3d9bada2408329269424628a3be6340c6c28de0e.zip | |
hw/arm/aspeed: change the FMC flash model of the AST2500 evb
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
to make the chip operate in 4 Byte address mode at power up. This
should be an interesting feature to model as it will exercise a bit
more the SMC controllers and MMIO execution at boot time.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180921161939.822-3-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/aspeed.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bb9590f1ae..f2d64e4551 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -105,7 +105,7 @@ static const AspeedBoardConfig aspeed_boards[] = { [AST2500_EVB] = { .soc_name = "ast2500-a1", .hw_strap1 = AST2500_EVB_HW_STRAP1, - .fmc_model = "n25q256a", + .fmc_model = "w25q256", .spi_model = "mx25l25635e", .num_cs = 1, .i2c_init = ast2500_evb_i2c_init, |