diff options
| author | Andrey Smirnov | 2019-07-01 18:26:15 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-07-01 18:28:59 +0200 |
| commit | 4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072 (patch) | |
| tree | e3a0f263e6f5d939dbbd2be8f6e5203aba2665a4 /hw | |
| parent | i.mx7d: Add no-op/unimplemented PCIE PHY IP block (diff) | |
| download | qemu-4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072.tar.gz qemu-4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072.tar.xz qemu-4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072.zip | |
pci: designware: Update MSI mapping unconditionally
Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:
!!root->msi.intr[0].enable ^ !!val;
so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/pci-host/designware.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 0fdfff5784..ec697c8f9d 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -297,16 +297,10 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, root->msi.base |= (uint64_t)val << 32; break; - case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: { - const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val; - + case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: root->msi.intr[0].enable = val; - - if (update_msi_mapping) { - designware_pcie_root_update_msi_mapping(root); - } + designware_pcie_root_update_msi_mapping(root); break; - } case DESIGNWARE_PCIE_MSI_INTR0_MASK: root->msi.intr[0].mask = val; |