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author | Blue Swirl | 2011-02-13 20:54:40 +0100 |
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committer | Blue Swirl | 2011-02-20 10:35:06 +0100 |
commit | 64d7e9a421fea0ac50b44541f5521de455e7cd5d (patch) | |
tree | e450cd7fd595ef79315ad131dd1d009b81935c69 /hw | |
parent | vga-isa: make optional (diff) | |
download | qemu-64d7e9a421fea0ac50b44541f5521de455e7cd5d.tar.gz qemu-64d7e9a421fea0ac50b44541f5521de455e7cd5d.tar.xz qemu-64d7e9a421fea0ac50b44541f5521de455e7cd5d.zip |
i8254: convert to qdev
Convert to qdev. Don't expose PITState.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/i8254.c | 61 | ||||
-rw-r--r-- | hw/mips_fulong2e.c | 4 | ||||
-rw-r--r-- | hw/mips_jazz.c | 4 | ||||
-rw-r--r-- | hw/mips_malta.c | 4 | ||||
-rw-r--r-- | hw/mips_r4k.c | 4 | ||||
-rw-r--r-- | hw/pc.c | 5 | ||||
-rw-r--r-- | hw/pc.h | 25 | ||||
-rw-r--r-- | hw/pcspk.c | 4 | ||||
-rw-r--r-- | hw/ppc_prep.c | 4 |
9 files changed, 75 insertions, 40 deletions
diff --git a/hw/i8254.c b/hw/i8254.c index 06b225cf4c..680caabf3c 100644 --- a/hw/i8254.c +++ b/hw/i8254.c @@ -53,9 +53,12 @@ typedef struct PITChannelState { qemu_irq irq; } PITChannelState; -struct PITState { +typedef struct PITState { + ISADevice dev; + uint32_t irq; + uint32_t iobase; PITChannelState channels[3]; -}; +} PITState; static PITState pit_state; @@ -119,8 +122,9 @@ static int pit_get_out1(PITChannelState *s, int64_t current_time) return out; } -int pit_get_out(PITState *pit, int channel, int64_t current_time) +int pit_get_out(ISADevice *dev, int channel, int64_t current_time) { + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s = &pit->channels[channel]; return pit_get_out1(s, current_time); } @@ -179,8 +183,9 @@ static int64_t pit_get_next_transition_time(PITChannelState *s, } /* val must be 0 or 1 */ -void pit_set_gate(PITState *pit, int channel, int val) +void pit_set_gate(ISADevice *dev, int channel, int val) { + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s = &pit->channels[channel]; switch(s->mode) { @@ -210,20 +215,23 @@ void pit_set_gate(PITState *pit, int channel, int val) s->gate = val; } -int pit_get_gate(PITState *pit, int channel) +int pit_get_gate(ISADevice *dev, int channel) { + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s = &pit->channels[channel]; return s->gate; } -int pit_get_initial_count(PITState *pit, int channel) +int pit_get_initial_count(ISADevice *dev, int channel) { + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s = &pit->channels[channel]; return s->count; } -int pit_get_mode(PITState *pit, int channel) +int pit_get_mode(ISADevice *dev, int channel) { + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s = &pit->channels[channel]; return s->mode; } @@ -462,9 +470,9 @@ static const VMStateDescription vmstate_pit = { } }; -static void pit_reset(void *opaque) +static void pit_reset(DeviceState *dev) { - PITState *pit = opaque; + PITState *pit = container_of(dev, PITState, dev.qdev); PITChannelState *s; int i; @@ -498,20 +506,39 @@ void hpet_pit_enable(void) pit_load_count(s, 0); } -PITState *pit_init(int base, qemu_irq irq) +static int pit_initfn(ISADevice *dev) { - PITState *pit = &pit_state; + PITState *pit = DO_UPCAST(PITState, dev, dev); PITChannelState *s; s = &pit->channels[0]; /* the timer 0 is connected to an IRQ */ s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); - s->irq = irq; + s->irq = isa_reserve_irq(pit->irq); - vmstate_register(NULL, base, &vmstate_pit, pit); - qemu_register_reset(pit_reset, pit); - register_ioport_write(base, 4, 1, pit_ioport_write, pit); - register_ioport_read(base, 3, 1, pit_ioport_read, pit); + register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit); + register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit); + isa_init_ioport(dev, pit->iobase); - return pit; + return 0; +} + +static ISADeviceInfo pit_info = { + .qdev.name = "isa-pit", + .qdev.size = sizeof(PITState), + .qdev.vmsd = &vmstate_pit, + .qdev.reset = pit_reset, + .qdev.no_user = 1, + .init = pit_initfn, + .qdev.props = (Property[]) { + DEFINE_PROP_UINT32("irq", PITState, irq, -1), + DEFINE_PROP_HEX32("iobase", PITState, iobase, -1), + DEFINE_PROP_END_OF_LIST(), + }, +}; + +static void pit_register(void) +{ + isa_qdev_register(&pit_info); } +device_init(pit_register) diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c index 2783ed5837..f5ae63980c 100644 --- a/hw/mips_fulong2e.c +++ b/hw/mips_fulong2e.c @@ -67,7 +67,7 @@ #define FULONG2E_ATI_SLOT 6 #define FULONG2E_RTL8139_SLOT 7 -static PITState *pit; +static ISADevice *pit; static struct _loaderparams { int ram_size; @@ -369,7 +369,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device, qdev_init_nofail(eeprom); /* init other devices */ - pit = pit_init(0x40, isa_reserve_irq(0)); + pit = pit_init(0x40, 0); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 85eba5a69a..a1003945fd 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -115,7 +115,7 @@ void mips_jazz_init (ram_addr_t ram_size, void* rc4030_opaque; int s_rtc, s_dma_dummy; NICInfo *nd; - PITState *pit; + ISADevice *pit; DriveInfo *fds[MAX_FD]; qemu_irq esp_reset, dma_enable; qemu_irq *cpu_exit_irq; @@ -181,7 +181,7 @@ void mips_jazz_init (ram_addr_t ram_size, isa_bus_irqs(i8259); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); - pit = pit_init(0x40, i8259[0]); + pit = pit_init(0x40, 0); pcspk_init(pit); /* ISA IO space at 0x90000000 */ diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 930c51c74d..ca6c6d7063 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -68,7 +68,7 @@ typedef struct { SerialState *uart; } MaltaFPGAState; -static PITState *pit; +static ISADevice *pit; static struct _loaderparams { int ram_size; @@ -930,7 +930,7 @@ void mips_malta_init (ram_addr_t ram_size, qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); qdev_init_nofail(eeprom); } - pit = pit_init(0x40, isa_reserve_irq(0)); + pit = pit_init(0x40, 0); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index fb34dcfcdc..8feb46163f 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -30,7 +30,7 @@ static const int ide_iobase[2] = { 0x1f0, 0x170 }; static const int ide_iobase2[2] = { 0x3f6, 0x376 }; static const int ide_irq[2] = { 14, 15 }; -static PITState *pit; /* PIT i8254 */ +static ISADevice *pit; /* PIT i8254 */ /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ @@ -274,7 +274,7 @@ void mips_r4k_init (ram_addr_t ram_size, isa_mmio_init(0x14000000, 0x00010000); isa_mem_base = 0x10000000; - pit = pit_init(0x40, i8259[0]); + pit = pit_init(0x40, 0); for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { @@ -1104,10 +1104,9 @@ void pc_basic_device_init(qemu_irq *isa_irq, { int i; DriveInfo *fd[MAX_FD]; - PITState *pit; qemu_irq rtc_irq = NULL; qemu_irq *a20_line; - ISADevice *i8042, *port92, *vmmouse; + ISADevice *i8042, *port92, *vmmouse, *pit; qemu_irq *cpu_exit_irq; register_ioport_write(0x80, 1, 1, ioport80_write, NULL); @@ -1128,7 +1127,7 @@ void pc_basic_device_init(qemu_irq *isa_irq, qemu_register_boot_set(pc_boot_set, *rtc_state); - pit = pit_init(0x40, isa_reserve_irq(0)); + pit = pit_init(0x40, 0); pcspk_init(pit); for(i = 0; i < MAX_SERIAL_PORTS; i++) { @@ -82,14 +82,23 @@ void isa_irq_handler(void *opaque, int n, int level); #define PIT_FREQ 1193182 -typedef struct PITState PITState; +static inline ISADevice *pit_init(int base, int irq) +{ + ISADevice *dev; + + dev = isa_create("isa-pit"); + qdev_prop_set_uint32(&dev->qdev, "iobase", base); + qdev_prop_set_uint32(&dev->qdev, "irq", irq); + qdev_init_nofail(&dev->qdev); + + return dev; +} -PITState *pit_init(int base, qemu_irq irq); -void pit_set_gate(PITState *pit, int channel, int val); -int pit_get_gate(PITState *pit, int channel); -int pit_get_initial_count(PITState *pit, int channel); -int pit_get_mode(PITState *pit, int channel); -int pit_get_out(PITState *pit, int channel, int64_t current_time); +void pit_set_gate(ISADevice *dev, int channel, int val); +int pit_get_gate(ISADevice *dev, int channel); +int pit_get_initial_count(ISADevice *dev, int channel); +int pit_get_mode(ISADevice *dev, int channel); +int pit_get_out(ISADevice *dev, int channel, int64_t current_time); void hpet_pit_disable(void); void hpet_pit_enable(void); @@ -159,7 +168,7 @@ void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); extern int no_hpet; /* pcspk.c */ -void pcspk_init(PITState *); +void pcspk_init(ISADevice *pit); int pcspk_audio_init(qemu_irq *pic); /* piix_pci.c */ diff --git a/hw/pcspk.c b/hw/pcspk.c index 26a0ecb9df..5f02908dac 100644 --- a/hw/pcspk.c +++ b/hw/pcspk.c @@ -37,7 +37,7 @@ typedef struct { uint8_t sample_buf[PCSPK_BUF_LEN]; QEMUSoundCard card; SWVoiceOut *voice; - PITState *pit; + ISADevice *pit; unsigned int pit_count; unsigned int samples; unsigned int play_pos; @@ -137,7 +137,7 @@ static void pcspk_ioport_write(void *opaque, uint32_t addr, uint32_t val) } } -void pcspk_init(PITState *pit) +void pcspk_init(ISADevice *pit) { PCSpkState *s = &pcspk_state; diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 6c1499a780..6c9826b59c 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -82,7 +82,7 @@ static const int ide_irq[2] = { 13, 13 }; static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; -//static PITState *pit; +//static ISADevice *pit; /* ISA IO ports bridge */ #define PPC_IO_BASE 0x80000000 @@ -662,7 +662,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* init basic PC hardware */ pci_vga_init(pci_bus); // openpic = openpic_init(0x00000000, 0xF0000000, 1); - // pit = pit_init(0x40, i8259[0]); + // pit = pit_init(0x40, 0); rtc_init(2000, NULL); if (serial_hds[0]) |