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authorPhilippe Mathieu-Daudé2018-03-08 23:39:37 +0100
committerPaolo Bonzini2018-03-12 16:12:49 +0100
commit7313b1f28bec390d03ec4b84146fbea43487f2ae (patch)
tree75b0e7d22614655fc81867b390551094ce5f486c /hw
parenthw/mips/malta: Code movement (diff)
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hw/isa/superio: Factor out the FDC37M817 Super I/O from mips_malta.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180308223946.26784-17-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/isa/isa-superio.c19
-rw-r--r--hw/mips/mips_malta.c35
2 files changed, 29 insertions, 25 deletions
diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c
index f98711beff..b95608a003 100644
--- a/hw/isa/isa-superio.c
+++ b/hw/isa/isa-superio.c
@@ -187,9 +187,28 @@ static const TypeInfo isa_superio_type_info = {
.class_init = isa_superio_class_init,
};
+/* SMS FDC37M817 Super I/O */
+static void fdc37m81x_class_init(ObjectClass *klass, void *data)
+{
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->serial.count = 2; /* NS16C550A */
+ sc->parallel.count = 1;
+ sc->floppy.count = 1; /* SMSC 82077AA Compatible */
+ sc->ide.count = 0;
+}
+
+static const TypeInfo fdc37m81x_type_info = {
+ .name = TYPE_FDC37M81X_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .instance_size = sizeof(ISASuperIODevice),
+ .class_init = fdc37m81x_class_init,
+};
+
static void isa_superio_register_types(void)
{
type_register_static(&isa_superio_type_info);
+ type_register_static(&fdc37m81x_type_info);
}
type_init(isa_superio_register_types)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 9e0724ca5a..f6513a4fd5 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -27,14 +27,12 @@
#include "cpu.h"
#include "hw/hw.h"
#include "hw/i386/pc.h"
+#include "hw/isa/superio.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
-#include "hw/char/parallel.h"
-#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/i2c/smbus.h"
-#include "sysemu/block-backend.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
@@ -47,7 +45,6 @@
#include "hw/loader.h"
#include "elf.h"
#include "hw/timer/mc146818rtc.h"
-#include "hw/input/i8042.h"
#include "hw/timer/i8254.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
@@ -1005,10 +1002,8 @@ void mips_malta_init(MachineState *machine)
qemu_irq cbus_irq, i8259_irq;
int piix4_devfn;
I2CBus *smbus;
- int i;
DriveInfo *dinfo;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
- DriveInfo *fd[MAX_FD];
int fl_idx = 0;
int fl_sectors = bios_size >> 16;
int be;
@@ -1023,15 +1018,6 @@ void mips_malta_init(MachineState *machine)
qdev_init_nofail(dev);
- /* Make sure the first 3 serial ports are associated with a device. */
- for(i = 0; i < 3; i++) {
- if (!serial_hds[i]) {
- char label[32];
- snprintf(label, sizeof(label), "serial%d", i);
- serial_hds[i] = qemu_chr_new(label, "null");
- }
- }
-
/* create CPU */
mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
@@ -1067,7 +1053,14 @@ void mips_malta_init(MachineState *machine)
#else
be = 0;
#endif
+
/* FPGA */
+
+ /* Make sure the second serial port is associated with a device. */
+ if (!serial_hds[2]) {
+ serial_hds[2] = qemu_chr_new("fpga-uart", "null");
+ }
+
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
@@ -1214,16 +1207,8 @@ void mips_malta_init(MachineState *machine)
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
g_free(smbus_eeprom_buf);
- /* Super I/O */
- isa_create_simple(isa_bus, TYPE_I8042);
-
- serial_hds_isa_init(isa_bus, 0, 2);
- parallel_hds_isa_init(isa_bus, 1);
-
- for(i = 0; i < MAX_FD; i++) {
- fd[i] = drive_get(IF_FLOPPY, 0, i);
- }
- fdctrl_init_isa(isa_bus, fd);
+ /* Super I/O: SMS FDC37M817 */
+ isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
/* Network card */
network_init(pci_bus);