diff options
| author | Chen Fan | 2016-02-19 17:42:28 +0100 |
|---|---|---|
| committer | Alex Williamson | 2016-02-19 17:42:28 +0100 |
| commit | 8d86ada2a7a2fe6d9f4209e042d2c5785fa5e0c1 (patch) | |
| tree | ed7828099c782eb80acbb216937a4f62d2a9ff9a /hw | |
| parent | vfio: make the 4 bytes aligned for capability size (diff) | |
| download | qemu-8d86ada2a7a2fe6d9f4209e042d2c5785fa5e0c1.tar.gz qemu-8d86ada2a7a2fe6d9f4209e042d2c5785fa5e0c1.tar.xz qemu-8d86ada2a7a2fe6d9f4209e042d2c5785fa5e0c1.zip | |
aer: impove pcie_aer_init to support vfio device
pcie_aer_init was used to emulate an aer capability for pcie device,
but for vfio device, the aer config space size is mutable and is not
always equal to PCI_ERR_SIZEOF(0x48). it depends on where the TLP Prefix
register required, so here we add a size argument.
Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/pci-bridge/ioh3420.c | 2 | ||||
| -rw-r--r-- | hw/pci-bridge/xio3130_downstream.c | 2 | ||||
| -rw-r--r-- | hw/pci-bridge/xio3130_upstream.c | 2 | ||||
| -rw-r--r-- | hw/pci/pcie_aer.c | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index 9e048ebe35..0937fa34be 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -126,7 +126,7 @@ static int ioh3420_initfn(PCIDevice *d) goto err_pcie_cap; } pcie_cap_root_init(d); - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET); + rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index c32f2712c8..cf1ee63aba 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -89,7 +89,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) goto err_pcie_cap; } pcie_cap_arifwd_init(d); - rc = pcie_aer_init(d, XIO3130_AER_OFFSET); + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 19798c09a8..164ef58c46 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -78,7 +78,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) } pcie_cap_flr_init(d); pcie_cap_deverr_init(d); - rc = pcie_aer_init(d, XIO3130_AER_OFFSET); + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index a9d9d06208..8043020444 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -95,12 +95,12 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log) aer_log->log_num = 0; } -int pcie_aer_init(PCIDevice *dev, uint16_t offset) +int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size) { PCIExpressDevice *exp; pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, - offset, PCI_ERR_SIZEOF); + offset, size); exp = &dev->exp; exp->aer_cap = offset; |