diff options
| author | Bin Meng | 2020-09-03 12:40:20 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | a4b84608ba0eecce1d4858181457dc26582e6d28 (patch) | |
| tree | c657deeba29792d6cda5b76235810d8763cc2497 /hw | |
| parent | hw/riscv: Move sifive_uart model to hw/char (diff) | |
| download | qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.gz qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.xz qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.zip | |
hw/riscv: Move sifive_test model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/misc/Kconfig | 3 | ||||
| -rw-r--r-- | hw/misc/meson.build | 1 | ||||
| -rw-r--r-- | hw/misc/sifive_test.c (renamed from hw/riscv/sifive_test.c) | 2 | ||||
| -rw-r--r-- | hw/riscv/Kconfig | 1 | ||||
| -rw-r--r-- | hw/riscv/meson.build | 1 | ||||
| -rw-r--r-- | hw/riscv/virt.c | 2 |
6 files changed, 7 insertions, 3 deletions
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fa3d0f4723..3185456110 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -134,6 +134,9 @@ config MAC_VIA config AVR_POWER bool +config SIFIVE_TEST + bool + config SIFIVE_E_PRCI bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 018a88c670..bd24132757 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) # RISC-V devices +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c index 8c70dd69df..2deb2072cc 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -25,7 +25,7 @@ #include "qemu/module.h" #include "sysemu/runstate.h" #include "hw/hw.h" -#include "hw/riscv/sifive_test.h" +#include "hw/misc/sifive_test.h" static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a0461578a6..8e0710001b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -61,6 +61,7 @@ config RISCV_VIRT select SIFIVE select SIFIVE_CLINT select SIFIVE_PLIC + select SIFIVE_TEST config MICROCHIP_PFSOC bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 967572d4f6..f762623288 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0caab8e050..41bd2f38ba 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" +#include "hw/misc/sifive_test.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" |