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| author | Paolo Bonzini | 2019-10-16 10:34:39 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2019-10-26 15:38:07 +0200 |
| commit | bf13bfab0840d34a74938ddf567d52e9010dbdc6 (patch) | |
| tree | 2743c5d7e769c7da29ddc7fcdb795a869514668e /hw | |
| parent | target/i386: introduce cpu_set_fpus (diff) | |
| download | qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.tar.gz qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.tar.xz qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.zip | |
i386: implement IGNNE
Change the handling of port F0h writes and FPU exceptions to implement IGNNE.
The implementation mixes a bit what the chipset and processor do in real
hardware, but the effect is the same as what happens with actual FERR#
and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering
FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i386/pc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c1a39de59f..96715f8a3f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -385,7 +385,7 @@ static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { if (tcg_enabled()) { - cpu_clear_ferr(); + cpu_set_ignne(); } } |