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authorJames Hogan2017-07-31 15:36:45 +0200
committerYongbok Kim2017-08-02 18:01:27 +0200
commitcb539fd241900f51de7d21244f7a55422ad0d40a (patch)
tree23aaedd50316634e5cd0cacc90e009caf0d8a025 /hw
parentUpdate version for v2.10.0-rc1 release (diff)
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target-mips: Don't stop on [d]mtc0 DESAVE/KScratch
Writing to the MIPS DESAVE register (and now the KScratch registers) will stop translation, supposedly due to risk of execution mode switches. However these registers are basically RW scratch registers with no side effects so there is no risk of them triggering execution mode changes. Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0. Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out the instruction decoding. This is also the first percent towards MIPS64 support.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions