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| author | Peter Crosthwaite | 2014-08-19 19:56:27 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-08-19 20:02:40 +0200 |
| commit | f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0 (patch) | |
| tree | 1ecd99b80f64f144a285fa3380d5642677245608 /hw | |
| parent | arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 (diff) | |
| download | qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.tar.gz qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.tar.xz qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.zip | |
arm: cortex-a9: Fix cache-line size and associativity
For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.
QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions