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author | Andrzej Jakowski | 2020-11-13 08:00:47 +0100 |
---|---|---|
committer | Klaus Jensen | 2021-02-08 21:15:53 +0100 |
commit | c7050631297f07917c23c7f4cdec8a6cca0eed12 (patch) | |
tree | 003d8a832ac300dc9b79ae9bd4e455db30951a21 /include/block/nvme.h | |
parent | hw/block/nvme: fix 64 bit register hi/lo split writes (diff) | |
download | qemu-c7050631297f07917c23c7f4cdec8a6cca0eed12.tar.gz qemu-c7050631297f07917c23c7f4cdec8a6cca0eed12.tar.xz qemu-c7050631297f07917c23c7f4cdec8a6cca0eed12.zip |
hw/block/nvme: indicate CMB support through controller capabilities register
This patch sets CMBS bit in controller capabilities register when user
configures NVMe driver with CMB support, so capabilites are correctly
reported to guest OS.
Signed-off-by: Andrzej Jakowski <andrzej.jakowski@linux.intel.com>
Reviewed-by: Maxim Levitsky <mlevitsky@gmail.com>
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'include/block/nvme.h')
-rw-r--r-- | include/block/nvme.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/include/block/nvme.h b/include/block/nvme.h index 854fb2abb6..151921da21 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -36,6 +36,7 @@ enum NvmeCapShift { CAP_MPSMIN_SHIFT = 48, CAP_MPSMAX_SHIFT = 52, CAP_PMR_SHIFT = 56, + CAP_CMB_SHIFT = 57, }; enum NvmeCapMask { @@ -49,6 +50,7 @@ enum NvmeCapMask { CAP_MPSMIN_MASK = 0xf, CAP_MPSMAX_MASK = 0xf, CAP_PMR_MASK = 0x1, + CAP_CMB_MASK = 0x1, }; #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -79,9 +81,11 @@ enum NvmeCapMask { #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ << CAP_MPSMIN_SHIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ - << CAP_MPSMAX_SHIFT) -#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ - << CAP_PMR_SHIFT) + << CAP_MPSMAX_SHIFT) +#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK) \ + << CAP_PMR_SHIFT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK) \ + << CAP_CMB_SHIFT) enum NvmeCapCss { NVME_CAP_CSS_NVM = 1 << 0, |