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| author | Aurelien Jarno | 2013-09-03 08:27:38 +0200 |
|---|---|---|
| committer | Richard Henderson | 2014-02-17 17:12:28 +0100 |
| commit | e46b225a3137e62c975c49aaae7bb5f9583cc428 (patch) | |
| tree | aba700db46bf9759e561945e7b4b753c27db4e80 /include/exec/memory-internal.h | |
| parent | tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]. (diff) | |
| download | qemu-e46b225a3137e62c975c49aaae7bb5f9583cc428.tar.gz qemu-e46b225a3137e62c975c49aaae7bb5f9583cc428.tar.xz qemu-e46b225a3137e62c975c49aaae7bb5f9583cc428.zip | |
tcg/optimize: fix known-zero bits for right shift ops
32-bit versions of sar and shr ops should not propagate known-zero bits
from the unused 32 high bits. For sar it could even lead to wrong code
being generated.
Cc: qemu-stable@nongnu.org
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'include/exec/memory-internal.h')
0 files changed, 0 insertions, 0 deletions