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| author | Palmer Dabbelt | 2019-06-24 10:59:51 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-26 07:32:42 +0200 |
| commit | 591bddea8d874e1500921de0353818e5586618f5 (patch) | |
| tree | 89a3ca7210f98e3cdf6bd85ac83c228c87b28262 /include/exec/memory.h | |
| parent | RISC-V: Add support for the Zifencei extension (diff) | |
| download | qemu-591bddea8d874e1500921de0353818e5586618f5.tar.gz qemu-591bddea8d874e1500921de0353818e5586618f5.tar.xz qemu-591bddea8d874e1500921de0353818e5586618f5.zip | |
RISC-V: Add support for the Zicsr extension
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/exec/memory.h')
0 files changed, 0 insertions, 0 deletions