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| author | Anup Patel | 2022-05-11 16:45:22 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-05-24 02:38:50 +0200 |
| commit | 24826da0eeacb27a5da6be764c8e853b2cede25b (patch) | |
| tree | a4a76c1553a23335db33ac3bd65d4055af4ce517 /include/exec/user | |
| parent | target/riscv: Fix csr number based privilege checking (diff) | |
| download | qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.tar.gz qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.tar.xz qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.zip | |
target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/exec/user')
0 files changed, 0 insertions, 0 deletions