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| author | Richard Henderson | 2019-05-18 20:37:02 +0200 |
|---|---|---|
| committer | Richard Henderson | 2019-05-22 21:09:43 +0200 |
| commit | 11e2bfef799024be4a08fcf6797fe0b22fb16b58 (patch) | |
| tree | 0a5cb2aec8d91f6e6cf68ce2b4962e831ef57314 /include/exec | |
| parent | tcg/aarch64: Allow immediates for vector ORR and BIC (diff) | |
| download | qemu-11e2bfef799024be4a08fcf6797fe0b22fb16b58.tar.gz qemu-11e2bfef799024be4a08fcf6797fe0b22fb16b58.tar.xz qemu-11e2bfef799024be4a08fcf6797fe0b22fb16b58.zip | |
tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store
This instruction raises #GP, aka SIGSEGV, if the effective address
is not aligned to 16-bytes.
We have assertions in tcg-op-gvec.c that the offset from ENV is
aligned, for vector types <= V128. But the offset itself does not
validate that the final pointer is aligned -- one must also remember
to use the QEMU_ALIGNED() attribute on the vector member within ENV.
PowerPC Altivec has vector load/store instructions that silently
discard the low 4 bits of the address, making alignment mistakes
difficult to discover. Aid that by making the most popular host
visibly signal the error.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions