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| author | Peter Maydell | 2017-03-20 13:41:44 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-03-20 13:41:44 +0100 |
| commit | 43ac65742319ef5ac4461daf43316b189cd21e89 (patch) | |
| tree | 002d91e680d68c84c9583073482b75adb38b02fb /include/exec | |
| parent | arm: HVC and SMC encodings don't exist for M profile (diff) | |
| download | qemu-43ac65742319ef5ac4461daf43316b189cd21e89.tar.gz qemu-43ac65742319ef5ac4461daf43316b189cd21e89.tar.xz qemu-43ac65742319ef5ac4461daf43316b189cd21e89.zip | |
arm: Don't decode MRS(banked) or MSR(banked) for M profile
M profile doesn't have the MSR(banked) and MRS(banked) instructions
and uses the encodings for different kinds of M-profile MRS/MSR.
Guard the relevant bits of the decode logic to make sure we don't
accidentally fall into them by accident on M-profile.
(The bit being checked for this (bit 5) is part of the SYSm field on
M-profile, but since no currently allocated system registers have
encodings with bit 5 of SYSm set, this hasn't been a problem in
practice.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions