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| author | Jim Wilson | 2019-03-15 11:26:59 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-03-19 13:13:24 +0100 |
| commit | 5371f5cd7170f29310575977f89e6e35d4d65168 (patch) | |
| tree | a280c7f86b3384f0590559191800771a898c8400 /include/exec | |
| parent | RISC-V: Add debug support for accessing CSRs. (diff) | |
| download | qemu-5371f5cd7170f29310575977f89e6e35d4d65168.tar.gz qemu-5371f5cd7170f29310575977f89e6e35d4d65168.tar.xz qemu-5371f5cd7170f29310575977f89e6e35d4d65168.zip | |
RISC-V: Add hooks to use the gdb xml files.
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
notice:
The fpu xml from gdb 8.3 has unused register #, 65 and make first
csr register # become 69. We register extra register on gdb to correct
csr offset calculation
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions
