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| author | Cédric Le Goater | 2019-11-19 15:11:58 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-12-16 11:46:34 +0100 |
| commit | 545d6bef7097129040bddc86fe09326ee0a14aae (patch) | |
| tree | c67e2474fd6a48e7373fe719d8147910b21d425a /include/exec | |
| parent | aspeed: Add a DRAM memory region at the SoC level (diff) | |
| download | qemu-545d6bef7097129040bddc86fe09326ee0a14aae.tar.gz qemu-545d6bef7097129040bddc86fe09326ee0a14aae.tar.xz qemu-545d6bef7097129040bddc86fe09326ee0a14aae.zip | |
aspeed/i2c: Add support for DMA transfers
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions