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| author | Peter Maydell | 2018-08-24 14:17:46 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-24 14:17:46 +0200 |
| commit | 7d3912f54e74a16dc69c1e427396ebef58ff4976 (patch) | |
| tree | e9fdca9f5cd3ee95650077d193c3fb037ad69947 /include/exec | |
| parent | hw/ssi/pl022: Correct wrong value for PL022_INT_RT (diff) | |
| download | qemu-7d3912f54e74a16dc69c1e427396ebef58ff4976.tar.gz qemu-7d3912f54e74a16dc69c1e427396ebef58ff4976.tar.xz qemu-7d3912f54e74a16dc69c1e427396ebef58ff4976.zip | |
hw/ssi/pl022: Correct wrong DMACR and ICR handling
In the PL022, register offset 0x20 is the ICR, a write-only
interrupt-clear register. Register offset 0x24 is DMACR, the DMA
control register. We were incorrectly implementing (a stub version
of) DMACR at 0x20, and not implementing anything at 0x24. Fix this
bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180820141116.9118-21-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions