diff options
| author | Rabin Vincent | 2014-05-01 16:24:44 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-05-01 16:24:44 +0200 |
| commit | e3da9921ebc554fad3224a9fdda9a7425ffd9ef7 (patch) | |
| tree | ffbf06134096b9031f25cf43cc1102a867d2cad5 /include/exec | |
| parent | target-arm: Implement XScale cache lockdown operations as NOPs (diff) | |
| download | qemu-e3da9921ebc554fad3224a9fdda9a7425ffd9ef7.tar.gz qemu-e3da9921ebc554fad3224a9fdda9a7425ffd9ef7.tar.xz qemu-e3da9921ebc554fad3224a9fdda9a7425ffd9ef7.zip | |
armv7m_nvic: fix CPUID Base Register
cp15.c0_cpuid is never initialized for ARMv7-M; take the value directly
from cpu->midr instead.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Message-id: 1398036308-32166-1-git-send-email-rabin@rab.in
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions