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authorBharata B Rao2017-01-06 07:14:49 +0100
committerDavid Gibson2017-01-31 00:10:14 +0100
commitf566c0474a9b9bbd9ed248607e4007e24d3358c0 (patch)
treea001e2d1b8fbb93c0e034374d5a08dea76affc8f /include/fpu
parenttarget-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 (diff)
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target-ppc: Add xscvdphp, xscvhpdp
xscvdphp: VSX Scalar round & Convert Double-Precision format to Half-Precision format xscvhpdp: VSX Scalar Convert Half-Precision format to Double-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/fpu')
-rw-r--r--include/fpu/softfloat.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 14f8383686..842ec6b22a 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -356,6 +356,26 @@ static inline int float16_is_any_nan(float16 a)
return ((float16_val(a) & ~0x8000) > 0x7c00);
}
+static inline int float16_is_neg(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+static inline int float16_is_infinity(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0x7c00;
+}
+
+static inline int float16_is_zero(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0;
+}
+
+static inline int float16_is_zero_or_denormal(float16 a)
+{
+ return (float16_val(a) & 0x7c00) == 0;
+}
+
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/