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| author | Richard Henderson | 2022-06-10 15:32:35 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-06-10 15:32:35 +0200 |
| commit | 6bcbb07af6a601b2521b07a639861218fbf0c87e (patch) | |
| tree | 881383c71e65e37dda854b617a91c98b6138172b /include/hw/acpi/acpi_aml_interface.h | |
| parent | target/arm: Adjust format test in scr_write (diff) | |
| download | qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.tar.gz qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.tar.xz qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.zip | |
target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
Since DDI0487F.a, the RW bit is RAO/WI. When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/acpi/acpi_aml_interface.h')
0 files changed, 0 insertions, 0 deletions