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authorPeter Maydell2016-10-04 14:48:25 +0200
committerPeter Maydell2016-10-04 14:48:25 +0200
commit6e11eb2d2b96790e647aa4c744ed2ed03a77fbbd (patch)
tree764d96006cedc488328f6c346115d4e2e423bd0e /include/hw/adc/stm32f2xx_adc.h
parentMerge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into st... (diff)
parenttarget-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' into staging
target-arm queue: * Netduino 2 improvements (SPI, ADC devices) * fix some Mainstone key mappings * vmstateify tsc210x, tsc2005 * virt: add 2.8 machine type * virt: support in-kernel GICv3 ITS * generic-loader device * A64: fix iss_sf decoding in disas_ld_lit * correctly handle 'sub pc, pc, 1' for ARMv6 # gpg: Signature made Tue 04 Oct 2016 13:41:34 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits) target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 target-arm: A64: Fix decoding of iss_sf in disas_ld_lit cadence_gem: Fix priority queue out of bounds access docs: Add a generic loader explanation document generic-loader: Add a generic loader ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table ACPI: Add GIC Interrupt Translation Service Structure definition arm/virt: Add ITS to the virt board hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation kvm-all: Pass requester ID to MSI routing functions target-arm: move gicv3_class_name from machine to kvm_arm.h hw/intc/arm_gicv3_its: Implement ITS base class hw/intc/arm_gic(v3)_kvm: Initialize gsi routing hw/arm/virt: add 2.8 machine type vmstateify tsc210x vmstateify tsc2005 hw/arm: Fix Integrator/CM initialization mainstone: Add mapping for dot, slash and backspace. mainstone: Fix incorrect key mapping for Enter key. MAINTAINERS: Add Alistair to the maintainers list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/adc/stm32f2xx_adc.h')
-rw-r--r--include/hw/adc/stm32f2xx_adc.h87
1 files changed, 87 insertions, 0 deletions
diff --git a/include/hw/adc/stm32f2xx_adc.h b/include/hw/adc/stm32f2xx_adc.h
new file mode 100644
index 0000000000..a72f734eb1
--- /dev/null
+++ b/include/hw/adc/stm32f2xx_adc.h
@@ -0,0 +1,87 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_ADC_H
+#define HW_STM32F2XX_ADC_H
+
+#define ADC_SR 0x00
+#define ADC_CR1 0x04
+#define ADC_CR2 0x08
+#define ADC_SMPR1 0x0C
+#define ADC_SMPR2 0x10
+#define ADC_JOFR1 0x14
+#define ADC_JOFR2 0x18
+#define ADC_JOFR3 0x1C
+#define ADC_JOFR4 0x20
+#define ADC_HTR 0x24
+#define ADC_LTR 0x28
+#define ADC_SQR1 0x2C
+#define ADC_SQR2 0x30
+#define ADC_SQR3 0x34
+#define ADC_JSQR 0x38
+#define ADC_JDR1 0x3C
+#define ADC_JDR2 0x40
+#define ADC_JDR3 0x44
+#define ADC_JDR4 0x48
+#define ADC_DR 0x4C
+
+#define ADC_CR2_ADON 0x01
+#define ADC_CR2_CONT 0x02
+#define ADC_CR2_ALIGN 0x800
+#define ADC_CR2_SWSTART 0x40000000
+
+#define ADC_CR1_RES 0x3000000
+
+#define ADC_COMMON_ADDRESS 0x100
+
+#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
+#define STM32F2XX_ADC(obj) \
+ OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t adc_sr;
+ uint32_t adc_cr1;
+ uint32_t adc_cr2;
+ uint32_t adc_smpr1;
+ uint32_t adc_smpr2;
+ uint32_t adc_jofr[4];
+ uint32_t adc_htr;
+ uint32_t adc_ltr;
+ uint32_t adc_sqr1;
+ uint32_t adc_sqr2;
+ uint32_t adc_sqr3;
+ uint32_t adc_jsqr;
+ uint32_t adc_jdr[4];
+ uint32_t adc_dr;
+
+ qemu_irq irq;
+} STM32F2XXADCState;
+
+#endif /* HW_STM32F2XX_ADC_H */