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| author | Peter Maydell | 2022-04-04 17:46:41 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-04-21 12:37:03 +0200 |
| commit | 2bd84b6818c790508a65ec34e268295c3cb9315f (patch) | |
| tree | 3b8b7732ab4f859e393dffddece7bcf88686fcaf /include/hw/arm | |
| parent | hw/arm: versal: Connect the CRL (diff) | |
| download | qemu-2bd84b6818c790508a65ec34e268295c3cb9315f.tar.gz qemu-2bd84b6818c790508a65ec34e268295c3cb9315f.tar.xz qemu-2bd84b6818c790508a65ec34e268295c3cb9315f.zip | |
hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line. We have a standard TYPE_OR_IRQ device for this now, so use
that instead.
(This is a migration compatibility break, but that is OK for this
machine type.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/exynos4210.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 60b9e126f5..3999034053 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -102,6 +102,7 @@ struct Exynos4210State { MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; }; #define TYPE_EXYNOS4210_SOC "exynos4210" |