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| author | Cédric Le Goater | 2022-06-30 09:21:13 +0200 |
|---|---|---|
| committer | Cédric Le Goater | 2022-06-30 09:21:13 +0200 |
| commit | 346160cbf2af4d946fd6cf84ef1f4fc5f1a422af (patch) | |
| tree | b13bf435d7ff03764c1c422a8a774aa0f4c9ba4a /include/hw/arm | |
| parent | hw: m25p80: add tests for write protect (WP# and SRWD bit) (diff) | |
| download | qemu-346160cbf2af4d946fd6cf84ef1f4fc5f1a422af.tar.gz qemu-346160cbf2af4d946fd6cf84ef1f4fc5f1a422af.tar.xz qemu-346160cbf2af4d946fd6cf84ef1f4fc5f1a422af.zip | |
aspeed: Set the dram container at the SoC level
Currently, the Aspeed machines allocate a ram container region in
which the machine ram region is mapped. See commit ad1a9782186d
("aspeed: add a RAM memory region container"). An extra region is
mapped after ram in the ram container to catch invalid access done by
FW. That's how FW determines the size of ram. See commit ebe31c0a8ef7
("aspeed: add a max_ram_size property to the memory controller").
Let's move all the logic under the SoC where it should be. It will
also ease the work on multi SoC support.
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220623202123.3972977-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/aspeed_soc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 02a5a9ffcb..e8a104823d 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -50,6 +50,7 @@ struct AspeedSoCState { A15MPPrivState a7mpcore; ARMv7MState armv7m; MemoryRegion *dram_mr; + MemoryRegion dram_container; MemoryRegion sram; AspeedVICState vic; AspeedRtcState rtc; @@ -165,5 +166,6 @@ enum { qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); void aspeed_soc_uart_init(AspeedSoCState *s); +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); #endif /* ASPEED_SOC_H */ |