diff options
| author | Havard Skinnemoen | 2020-10-23 23:06:37 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-27 12:10:32 +0100 |
| commit | 526dbbe087475599589ada4df70a337c09ae0f3f (patch) | |
| tree | e952fde2b6f45bb9bdb891998a9fa71c16b0bb67 /include/hw/arm | |
| parent | hw/arm/npcm7xx: Add EHCI and OHCI controllers (diff) | |
| download | qemu-526dbbe087475599589ada4df70a337c09ae0f3f.tar.gz qemu-526dbbe087475599589ada4df70a337c09ae0f3f.tar.xz qemu-526dbbe087475599589ada4df70a337c09ae0f3f.zip | |
hw/gpio: Add GPIO model for Nuvoton NPCM7xx
The NPCM7xx chips have multiple GPIO controllers that are mostly
identical except for some minor differences like the reset values of
some registers. Each controller controls up to 32 pins.
Each individual pin is modeled as a pair of unnamed GPIOs -- one for
emitting the actual pin state, and one for driving the pin externally.
Like the nRF51 GPIO controller, a gpio level may be negative, which
means the pin is not driven, or floating.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/npcm7xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index aeee1beaaa..5469247e38 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -18,6 +18,7 @@ #include "hw/boards.h" #include "hw/cpu/a9mpcore.h" +#include "hw/gpio/npcm7xx_gpio.h" #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" @@ -79,6 +80,7 @@ typedef struct NPCM7xxState { NPCM7xxOTPState fuse_array; NPCM7xxMCState mc; NPCM7xxRNGState rng; + NPCM7xxGPIOState gpio[8]; EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; |