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author | Francisco Iglesias | 2022-01-21 17:11:38 +0100 |
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committer | Peter Maydell | 2022-01-28 15:29:46 +0100 |
commit | 868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3 (patch) | |
tree | edf617755651176c094cda54d5d76cf0ae7097a7 /include/hw/arm | |
parent | hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller (diff) | |
download | qemu-868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3.tar.gz qemu-868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3.tar.xz qemu-868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3.zip |
hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220121161141.14389-8-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm')
-rw-r--r-- | include/hw/arm/xlnx-versal.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 811df73350..1b5ad4de80 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -26,6 +26,8 @@ #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-versal-efuse.h" +#include "hw/ssi/xlnx-versal-ospi.h" +#include "hw/dma/xlnx_csu_dma.h" #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" #define TYPE_XLNX_VERSAL "xlnx-versal" @@ -80,6 +82,14 @@ struct Versal { struct { SDHCIState sd[XLNX_VERSAL_NR_SDS]; XlnxVersalPmcIouSlcr slcr; + + struct { + XlnxVersalOspi ospi; + XlnxCSUDMA dma_src; + XlnxCSUDMA dma_dst; + MemoryRegion linear_mr; + qemu_or_irq irq_orgate; + } ospi; } iou; XlnxZynqMPRTC rtc; @@ -116,6 +126,7 @@ struct Versal { #define VERSAL_ADMA_IRQ_0 60 #define VERSAL_XRAM_IRQ_0 79 #define VERSAL_PMC_APB_IRQ 121 +#define VERSAL_OSPI_IRQ 124 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 @@ -184,6 +195,15 @@ struct Versal { #define MM_PMC_PMC_IOU_SLCR 0xf1060000 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 +#define MM_PMC_OSPI 0xf1010000 +#define MM_PMC_OSPI_SIZE 0x10000 + +#define MM_PMC_OSPI_DAC 0xc0000000 +#define MM_PMC_OSPI_DAC_SIZE 0x20000000 + +#define MM_PMC_OSPI_DMA_DST 0xf1011800 +#define MM_PMC_OSPI_DMA_SRC 0xf1011000 + #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 |