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| author | Peter Maydell | 2021-02-19 15:45:54 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:02 +0100 |
| commit | 91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688 (patch) | |
| tree | d61c28c9b002825bf9e2c025b95414a31774d884 /include/hw/arm | |
| parent | hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block (diff) | |
| download | qemu-91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688.tar.gz qemu-91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688.tar.xz qemu-91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688.zip | |
hw/arm/armsse: Use an array for apb_ppc fields in the state structure
Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct
to use an array instead of two separate fields. We already had one
place in the code that wanted to be able to refer to the PPC by
index, and we're about to add more code like that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-22-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/armsse.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 09284ca75c..771150b0a9 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -124,8 +124,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs */ +#define NUM_INTERNAL_PPCS 2 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) -#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) +#define NUM_PPCS (NUM_EXTERNAL_PPCS + NUM_INTERNAL_PPCS) #define MAX_SRAM_BANKS 4 #if MAX_SRAM_BANKS > IOTS_NUM_MPC @@ -152,8 +153,7 @@ struct ARMSSE { ARMv7MState armv7m[SSE_MAX_CPUS]; CPUClusterState cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; - TZPPC apb_ppc0; - TZPPC apb_ppc1; + TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTimer timer0; CMSDKAPBTimer timer1; |