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| author | Peter Maydell | 2021-02-19 15:46:05 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:03 +0100 |
| commit | 9febd175415dbc84e6ff7bda9bf6d90fe060181e (patch) | |
| tree | 327e6c25c170d1c7a716139ce7df0ad9926f4362 /include/hw/arm | |
| parent | hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo (diff) | |
| download | qemu-9febd175415dbc84e6ff7bda9bf6d90fe060181e.tar.gz qemu-9febd175415dbc84e6ff7bda9bf6d90fe060181e.tar.xz qemu-9febd175415dbc84e6ff7bda9bf6d90fe060181e.zip | |
hw/arm/armsse: Add support for SSE variants with a system counter
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has the counter in a different location.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-33-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/armsse.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 104ba8d26e..149f17dfc8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -97,6 +97,7 @@ #include "hw/misc/tz-mpc.h" #include "hw/timer/cmsdk-apb-timer.h" #include "hw/timer/cmsdk-apb-dualtimer.h" +#include "hw/timer/sse-counter.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" @@ -164,6 +165,8 @@ struct ARMSSE { CMSDKAPBWatchdog cmsdk_watchdog[3]; + SSECounter sse_counter; + IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; |