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| author | Peter Maydell | 2021-05-10 21:08:44 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-05-25 17:01:43 +0200 |
| commit | cbb563887781d813e67c59b68dd76891cb78c3d4 (patch) | |
| tree | ac2693dfaeadc55ae0c9e02f30f0b32dc2b1552e /include/hw/arm | |
| parent | hw/arm/mps2-tz: Allow board to specify a boot RAM size (diff) | |
| download | qemu-cbb563887781d813e67c59b68dd76891cb78c3d4.tar.gz qemu-cbb563887781d813e67c59b68dd76891cb78c3d4.tar.xz qemu-cbb563887781d813e67c59b68dd76891cb78c3d4.zip | |
hw/arm: Model TCMs in the SSE-300, not the AN547
The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000.
Currently we model these in the AN547 board, but this is conceptually
wrong, because they are a part of the SSE-300 itself. Move the
modelling of the TCMs out of mps2-tz.c into sse300.c.
This has no guest-visible effects.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-7-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/armsse.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 36592be62c..9648e7a419 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -198,6 +198,8 @@ struct ARMSSE { MemoryRegion alias2; MemoryRegion alias3[SSE_MAX_CPUS]; MemoryRegion sram[MAX_SRAM_BANKS]; + MemoryRegion itcm; + MemoryRegion dtcm; qemu_irq *exp_irqs[SSE_MAX_CPUS]; qemu_irq ppc0_irq; |