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authorCédric Le Goater2019-07-01 18:26:15 +0200
committerPeter Maydell2019-07-01 18:28:59 +0200
commitd783d1fe581dc250dcc44e629f2f52f617920465 (patch)
treef27e0704c318682db7bb6a868346e0d343f2c94c /include/hw/arm
parentaspeed: add a per SoC mapping for the interrupt space (diff)
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aspeed: add a per SoC mapping for the memory space
This will simplify the definition of new SoCs, like the AST2600 which should use a slightly different address space and have a different set of controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm')
-rw-r--r--include/hw/arm/aspeed_soc.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 963abecb72..88b901d5df 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -49,14 +49,13 @@ typedef struct AspeedSoCInfo {
const char *name;
const char *cpu_type;
uint32_t silicon_rev;
- hwaddr sdram_base;
uint64_t sram_size;
int spis_num;
- const hwaddr *spi_bases;
const char *fmc_typename;
const char **spi_typename;
int wdts_num;
const int *irqmap;
+ const hwaddr *memmap;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {
@@ -102,6 +101,7 @@ enum {
ASPEED_I2C,
ASPEED_ETH1,
ASPEED_ETH2,
+ ASPEED_SDRAM,
};
#endif /* ASPEED_SOC_H */