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| author | Luc Michel | 2020-10-10 15:57:56 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-27 12:10:44 +0100 |
| commit | 502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7 (patch) | |
| tree | db3f113ffa05bf1b95d691fa67c1d1eebf805dc0 /include/hw/char | |
| parent | hw/misc/bcm2835_cprman: implement clock mux behaviour (diff) | |
| download | qemu-502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7.tar.gz qemu-502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7.tar.xz qemu-502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7.zip | |
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/char')
0 files changed, 0 insertions, 0 deletions