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| author | Bin Meng | 2020-09-03 12:40:17 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 84fcf3c15111de9f0c72efbb6bc0def264555c46 (patch) | |
| tree | 57567c453d5ea85f06f0c753aefa4fa0d9709eae /include/hw/char | |
| parent | hw/riscv: Move sifive_clint model to hw/intc (diff) | |
| download | qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.tar.gz qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.tar.xz qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.zip | |
hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/char')
0 files changed, 0 insertions, 0 deletions