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| author | Tony Nguyen | 2019-08-23 20:36:57 +0200 |
|---|---|---|
| committer | Richard Henderson | 2019-09-03 17:30:39 +0200 |
| commit | 9bed46e67e2ee54bc596ba58063ee71a5ca40923 (patch) | |
| tree | 719c2d7c2cc1b300b66de0f7fdbfe98a524f44b1 /include/hw/core/cpu.h | |
| parent | cputlb: Byte swap memory transaction attribute (diff) | |
| download | qemu-9bed46e67e2ee54bc596ba58063ee71a5ca40923.tar.gz qemu-9bed46e67e2ee54bc596ba58063ee71a5ca40923.tar.xz qemu-9bed46e67e2ee54bc596ba58063ee71a5ca40923.zip | |
target/sparc: Add TLB entry with attributes
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <f8fcc3138570c460ef289a6b34ba7715ba36f99e.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw/core/cpu.h')
0 files changed, 0 insertions, 0 deletions