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authorBin Meng2022-04-21 02:33:24 +0200
committerAlistair Francis2022-04-22 02:35:16 +0200
commit013577de8f52fc64d77d1c13d69150b5902420d9 (patch)
tree8d3ac9eb17c1e8d4a25faa0bab077d9e72b7d383 /include/hw/core
parenttarget/riscv: cpu: Enable native debug feature (diff)
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hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/core')
-rw-r--r--include/hw/core/tcg-cpu-ops.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index fbe6b76764..78c6c6635d 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);