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| author | Bin Meng | 2020-09-01 03:39:02 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:18 +0200 |
| commit | c696e1f2b392af19653e82da26df3c61b85ab5a2 (patch) | |
| tree | 1fd7a96bbc40a5bf5aae06f7de551b684876c443 /include/hw/dma | |
| parent | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs (diff) | |
| download | qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.tar.gz qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.tar.xz qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.zip | |
hw/sd: Add Cadence SDHCI emulation
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/dma')
0 files changed, 0 insertions, 0 deletions