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| author | Peter Xu | 2019-03-13 10:43:23 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2019-03-20 11:44:13 +0100 |
| commit | 4b519ef1de9a7cb8123abadab9e6c5697373087c (patch) | |
| tree | 2c12938a5b20a2f6fc7c5d1e33f7aa43e5156ec5 /include/hw/i386 | |
| parent | test-announce-self: convert to qgraph (diff) | |
| download | qemu-4b519ef1de9a7cb8123abadab9e6c5697373087c.tar.gz qemu-4b519ef1de9a7cb8123abadab9e6c5697373087c.tar.xz qemu-4b519ef1de9a7cb8123abadab9e6c5697373087c.zip | |
intel-iommu: optimize nodmar memory regions
Previously we have per-device system memory aliases when DMAR is
disabled by the system. It will slow the system down if there are
lots of devices especially when DMAR is disabled, because each of the
aliased system address space will contain O(N) slots, and rendering
such N address spaces will be O(N^2) complexity.
This patch introduces a shared nodmar memory region and for each
device we only create an alias to the shared memory region. With the
aliasing, QEMU memory core API will be able to detect when devices are
sharing the same address space (which is the nodmar address space)
when rendering the FlatViews and the total number of FlatViews can be
dramatically reduced when there are a lot of devices.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Message-Id: <20190313094323.18263-1-peterx@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/hw/i386')
| -rw-r--r-- | include/hw/i386/intel_iommu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index c11e3d5b34..536f62667b 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -105,8 +105,8 @@ struct VTDAddressSpace { uint8_t devfn; AddressSpace as; IOMMUMemoryRegion iommu; - MemoryRegion root; - MemoryRegion sys_alias; + MemoryRegion root; /* The root container of the device */ + MemoryRegion nodmar; /* The alias of shared nodmar MR */ MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; @@ -221,6 +221,9 @@ union VTD_IR_MSIAddress { struct IntelIOMMUState { X86IOMMUState x86_iommu; MemoryRegion csrmem; + MemoryRegion mr_nodmar; + MemoryRegion mr_ir; + MemoryRegion mr_sys_alias; uint8_t csr[DMAR_REG_SIZE]; /* register values */ uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ |