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| author | Peter Maydell | 2016-07-14 18:32:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-07-14 18:32:53 +0200 |
| commit | 14c7d99333e4a474c65bdae6f99aa8837e8078e6 (patch) | |
| tree | 32c8874413f0ab109176d649557e1eb63c053805 /include/hw/intc | |
| parent | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-fwcfg' into s... (diff) | |
| parent | ast2400: externalize revision numbers (diff) | |
| download | qemu-14c7d99333e4a474c65bdae6f99aa8837e8078e6.tar.gz qemu-14c7d99333e4a474c65bdae6f99aa8837e8078e6.tar.xz qemu-14c7d99333e4a474c65bdae6f99aa8837e8078e6.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160714' into staging
target-arm queue:
* add virtio-mmio transport base address to device path
(avoid an assertion failure with multiple virtio-scsi-devices)
* revert hw/ptimer commit 5a50307 which causes regressions on
SPARC guests
* use Neon to accelerate zero-page checking on AArch64 hosts
* set the MPIDR for TCG to match how KVM does it (and fit with
GICv2/GICv3 restrictions on SGI target lists)
* add some missing AArch32 TLBI hypervisor TLB operations
* m25p80: Fix QIOR/DIOR handling for Winbond
* hw/misc: fix typo in Aspeed SCU hw-strap2 property name
* ast2400: pretend DMAs are done for U-boot
* ast2400: some minor code cleanups
# gpg: Signature made Thu 14 Jul 2016 17:21:30 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20160714:
ast2400: externalize revision numbers
ast2400: pretend DMAs are done for U-boot
ast2400: replace aspeed_smc_is_implemented()
hw/misc: fix typo in Aspeed SCU hw-strap2 property name
m25p80: Fix QIOR/DIOR handling for Winbond
target-arm: Add missed AArch32 TLBI sytem registers
hw/arm/virt: tcg: adjust MPIDR like KVM
gic: provide defines for v2/v3 targetlist sizes
target-arm: Use Neon for zero checking
Revert "hw/ptimer: Perform counter wrap around if timer already expired"
virtio-mmio: format transport base address in BusClass.get_dev_path
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/intc')
| -rw-r--r-- | include/hw/intc/arm_gic.h | 3 | ||||
| -rw-r--r-- | include/hw/intc/arm_gicv3_common.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 0971e37710..42bb535fd4 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -23,6 +23,9 @@ #include "arm_gic_common.h" +/* Number of SGI target-list bits */ +#define GIC_TARGETLIST_BITS 8 + #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index f72e49922f..341a3118f0 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -35,6 +35,9 @@ #define GICV3_MAXIRQ 1020 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) +/* Number of SGI target-list bits */ +#define GICV3_TARGETLIST_BITS 16 + /* Minimum BPR for Secure, or when security not enabled */ #define GIC_MIN_BPR 0 /* Minimum BPR for Nonsecure when security is enabled */ |