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| author | Julia Suvorova | 2018-08-14 18:17:19 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-14 18:17:19 +0200 |
| commit | 22ab3460017cfcfb6b50f05838ad142e08becce5 (patch) | |
| tree | 785a9721a6e4a75b6878ded40e11d886b399de05 /include/hw/intc | |
| parent | nvic: Handle ARMv6-M SCS reserved registers (diff) | |
| download | qemu-22ab3460017cfcfb6b50f05838ad142e08becce5.tar.gz qemu-22ab3460017cfcfb6b50f05838ad142e08becce5.tar.xz qemu-22ab3460017cfcfb6b50f05838ad142e08becce5.zip | |
arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as a HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20180718095628.26442-1-jusual@mail.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/intc')
0 files changed, 0 insertions, 0 deletions