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| author | Frank Chang | 2022-04-20 10:08:58 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-04-22 02:35:16 +0200 |
| commit | d42df0ea5dd58cfda5e1466487f93b5b90a67594 (patch) | |
| tree | d3491de7164e8c661d83821f3665e484364d88c5 /include/hw/intc | |
| parent | hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT (diff) | |
| download | qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.tar.gz qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.tar.xz qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.zip | |
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to perform both 32/64-bit read/write accesses to both
mtimecmp and mtime registers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/intc')
0 files changed, 0 insertions, 0 deletions